The present invention relates to memory coherency in a processor-to-bus cycles in a multi-processor system.
Many computer systems include multiple processors, such as central processing units (CPUs), which may perform various operations requiring access to a main memory. Examples include reading or writing data from or to the main memory. In these systems, several CPUs may perform operations with respect to data stored in a particular main memory address during the same time interval. Furthermore, a particular CPU may retrieve data from the main memory, modify the retrieved data, and then write the modified data to the specified main memory address.
To enhance the speed capabilities of the system, many computer systems have cache memories associated with the CPUs in addition to the system's main memory. The cache memories are used for the temporary storage of data which the CPUs use during performance of various other operations.
Data is typically transferred between the main memory and the CPUs through one or more buses. A central processor controls access to the bus and determines which CPU or other system component will be given access to the bus at any given time. The central processor thus allows specified bus or memory cycles to be performed before performance of other cycles involving the storage, retrieval and transmission of data from one system component to another system component. One purpose of such priority techniques is to ensure that data stored in the main memory does not become stale. These priority techniques thus help prevent one system component from accessing data in the main memory which was previously modified by another system component but which has not yet returned to the main memory.